Flexible Electronics
Flexible electronics, having no common current collector, are predominantly produced by ink-jet or screen printing of metal and carbon pastes over a flexible substrate. Having inferior conductivity compared to pure metals, metal pastes are usually significantly thicker than the pure metal. The process is complex, including solvents and high temperature treatments of pastes and polymer structures to achieve functional products. Typically, inferior property of the metal pastes (such as low conductivity and excessive thickness) limit the progress of the industry, particularly in the field of high density flexible electronics.
To optimize the process, another approach to flexible electronics involves sintering of metal nanoparticles, such as silver. For example, U.S. Pat. No. 9,343,233 describes a method of depositing suspension of silver nanoparticles followed by sintering at 170-180° C. for 30 to 40 minutes. Again, the process remains complex and time-consuming and includes pushing the substrate performance to the limits.
More recently, efforts have been made to eliminate chemical and thermal processing of the pastes. For example, T. Zhang et al. (“A Laser Printing Based Approach for Printed Electronic”, Applied Physics Letters 108, 103501 (2016)) introduce the technique of electroless plating of substrate layers coated with electroless process catalysts, such as palladium. The technique involves patterning the substrate using laser selected deposition of palladium catalyst-modified toner, melting and fusing it onto the substrate, and then completing the process by electroless deposition of desired metal (e.g., copper). While much progress has been made in the fields of electroless and immersion plating, both processes are extremely slow and prone to failure due to the lack of direct control by the operator. That is, both processes are spontaneous and hard to control and maintain, thereby delivering metals of inferior properties (i.e., metals with porosity and occlusion issues). Moreover, while removing undesirable steps from prior art processing, the T. Zhang et. al. approach introduces new steps that appear to make the process more complex and potentially slowing it down significantly, with electroless deposition rate in the range of just few nanometers per second.
Surface Finishing
Similarly, surface finishing (such as electroless and/or immersion finishing of PWB and discrete electronic devices) is typically applied on electronic circuitry or devices that have nearly been completed. In the prior art, surface finishing is applied after the common current collector has been removed and the circuitry or devices become electrically isolated. Thus, the prior art technology/method of providing electroplating current to the points of surface finishing is not applicable.
Hence, it would be useful to provide an electroplating apparatus and method capable of replacing application of metal pastes and standard electroless and immersion technology with pure metals on PWBs, flexible electronics, and discrete electronic devices.
IC Processing
In many electroplating processes, there is a need to electroplate a multitude of micro and nano isolated structures simultaneously across the large patterned area. In order to overcome the problem of establishing electrical contacts to all structures on the substrate, the prior art utilizes the so called “seed layer” (SL). Typically, the SL is made of a thin coating (one micron or less) of gold, silver, or copper deposited by CV or plasma deposition—or by similar techniques providing conductive but lower grade metal. Having a SL of minimal resistance itself and all structures patterned and defined on top of the SL or carved as trenches in the substrate and thus electrically interconnected, they can now be electroplated simultaneously. The problem arises from the need to provide uniform electrical current to features that are several centimeters to several decimeters away from the closest peripheral heavy gauge contact with the power supply. In particular, that becomes evident in IC fabrication. Damascene and dual damascene nano-size structures, calling for only 10 plus nano-meters wide and high features carved/etched in the substrate, can preferably utilize an SL of less than several nanometer thicknesses. Otherwise, a 10 plus nano meter or 1000 nm thick low grade SL would defeat the design specs for the IC structure of high grade metal 10 plus nanometers total. Thus, it becomes impractical to deposit thicker SL, needed for sufficient current carrying capability, with the goal of 10 plus nanometer size electroplated IC device. Consequently, due to a limited current carrying capability of such thin SL, a significant problem arises of simultaneously growing a multitude of micro and nano structures over large surface areas of substrate. To overcome this problem, several examples are described in U.S. Pat. Nos. 7,449,098; 7,947,157; and 8,071,468, which show the trenches, defined by the design of the ICs, that are produced by multiple interchangeable iterations of electroplating and polishing (chemical-mechanical planarization, CMP) due to uneven growth of deposit across the substrate. Hence, a method capable of bypassing peripheral contact and delivering simultaneous electrical contact to each section of the substrate regardless of the SL resistivity and enabling uniform growth of deposits across the substrate would be desirable. In addition, the method offers the capability to eliminate peripheral electrical contact, a complex structural section of each IC electroplating device utilized in the state-of-the-art technology. Furthermore, current trends to three dimensional structures including multilayered devices involve complex design and fabrication steps to enable electroplating for each layer of the stack. Direct access to each seed layer or patterns of the stack by the disclosed device can simplify the process and enable significantly more practical solutions.